NXP Semiconductors /LPC43xx /ADCHS /DESCRIPTOR0_[7]

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Interpret as DESCRIPTOR0_[7]

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CHANNEL_NR 0 (HALT)HALT 0 (INTERRUPT)INTERRUPT 0 (POWER_DOWN)POWER_DOWN 0BRANCH 0MATCH_VALUE0THRESHOLD_SEL 0 (RESET_TIMER)RESET_TIMER 0RESERVED0 (UPDATE_TABLE)UPDATE_TABLE

Description

Table 0 descriptor n, n= 0 to 7

Fields

CHANNEL_NR

0: convert input 0 1: convert input 1 2: convert input 2 3: convert input 3 4: convert input 4 5: convert input 5 6,7: reserved

HALT

0: After this descriptor continue with the next descriptor. 1: halt after this descriptor is processed. Restart at a new trigger.

INTERRUPT

1: Raise interrupt when ADC result is available

POWER_DOWN

1: Power down after this conversion.

BRANCH

00: Continue with next descriptor (wraps around after top). 01: Branch to the first descriptor in this table. 10: Swap tables and branch to the first descriptor of the new table. 11: reserved (do not store sample). Continue with next descriptor (wraps around after top).

MATCH_VALUE

Evaluate this descriptor when descriptor timer value is equal to match value.

THRESHOLD_SEL

Indicates which threshold comparison level register set is to be used: 00: no comparison, 01: THR_A. 10: THR_B. 11: Reserved

RESET_TIMER

1: reset descriptor timer.

RESERVED

Reserved

UPDATE_TABLE

1: Update table with all 8 descriptors of this table. Descriptors of this table that are written without this bit set are not updated until any descriptor of this table is written with this bit set. This field is write only. A read returns 0x0.

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